Course Description

Physical design is an integral part of development of digital hardware. The content taught in this course will help the students to plan and execute implementations of systems like processors, advanced VLSI systems design and physical layers of communications. The objectives of this course can be summarized below:

• Understand the background in CMOS and devices, representing them in behavioral, structural, and physical domain and how it differs from an analog circuit implementation
• Understand the concepts of Physical Design Process such as partitioning, floor planning, placement and routing
• Get an introduction to the concepts of design optimization algorithms and their application to Physical Design Automation
• Understand the concepts of simulation and synthesis in VLSI Design Automation (using standard cells, FPGAs, etc.)
• Be able to formulate challenges in a realistic IC design and figure out the steps to solve/mitigate them
• Understand how the CAD tools work to facilitate the IC design (in a nutshell)

Apart from providing backgrounds, the course offers a hands-on training to practice the acquired theoretical knowledge. This includes access to the tools used for physical design and to design a small digital chip. Basic Verilog programming knowledge will be needed to follow this practical part.

Course Contents

• Introduction
• Digital design and standard cells (different technologies)
• Netlisting and system portioning
• Floorplanning
• Routing and placement (block level, chip level)
• Timing analysis and performance constraints
• Clock tree analysis and signal integrity
• Timing-driven placement and routing leading to Physical synthesis
• DRC related to Physical Synthesis
• Parasitic Extraction
• Designing a small digital chip
   

Proposal for credit points: 6 credit points
2/0/1 course: 2 hours/week lectures, 1 hour/week practical training, and self-study
The course grade is the weighted mean of the grade from the report weighted by 2/3 and the grade of the presentation weighted by 1/3. 

Responsible Persons: