The group Scalable Computing Hardware develops a scalable multiprocessor system-on-chip (MPSoC) which enables secure and energy-efficient data processing for applications of the internet of things (IoT). We investigate security concepts in MPSoC architectures to isolate various parallel applications and to minimize the impact of malicious attacks or software faults. The processor platform provides the necessary hardware components for a microkernel-based operating system which will be integrated in close collaboration with the group Composable Operating Systems within the research topic Composability of HW/SW. The MPSoC is realized as FPGA implementation as well as a silicon research chip.Introduction text about your group.
F. Pauls, R. Wittig, G. Fettweis: A Latency-Optimized Hash-Based Digital Signature Accelerator for the Tactile Internet. International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), Greece, July 2019
G. Fettweis, E. Matus, R. Wittig, M. Hasler, S. Damjancevic, S. Nam and S. Haas: 5G-and-Beyond Scalable Machines. 27th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Cuzco, Peru, Oct. 2019
G. Fettweis, E. Matus, R. Wittig, M. Hasler, S. Damjancevic, S. Haas, F. Pauls, S. Nam, N. Grigoryan: A Low-Power Scalable Signal Processing Chip Platform for 5G and Beyond - Kachel. 53rd Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, Nov. 2019