We expect the following:
- Above-average MSc/Diploma degrees in areas related to our research focus (Electrical/Computer Engineering) from renowned universities.
- Good communication and writing skills in English.
- An integrative and cooperative personality with excellent communication and social skills.
- Knowledge in programming with C/C++, Python, Verilog/VHDL.
- Experience of SoC design flow including software tools from Cadence and Synopsys.
You will join a team of enthusiastic scientists who creatively pursue our research agenda. Your responsibilities will include
- Design and development of digital hardware for ASIC and FPGA implementations
- HDL simulation and verification including embedded software programming
- Support of SoC design projects through tape-out with focus on one or multiple of the following: RTL synthesis, DFT insertion, verification/testing, design planning, physical optimization, timing analysis/closure, design integrity checking
(Training to perform above tasks will be given as needed)
Application Procedure: Your application should include: motivation letter, CV, copy of university degree certificate, short summary of Master thesis. Applications from women are particularly welcome. Complete applications should be submitted by e-mail as a single PDF document to email@example.com. Informal inquiries can also be submitted to the same address.